In certain types of computer memory, respective binary data is stored as a voltage level, i.e., high or low, in a number of storage cells. The storage cells are generally defined to accept a voltage level to be stored in a write operation, and drive a voltage stored therein in a read operation. More specifically, in a read operation of a particular storage cell, the voltage level present in the particular storage cell is driven on a pair of bitlines to a sense amplifier. When activated, i.e., enabled, the sense amplifier is defined to determine a voltage level present on the bitlines, and thereby determine the logic state of the binary data present in the storage cell.
A sense enable signal is transmitted to the sense amplifier to enable sensing of the bitlines connected to the sense amplifier. The data on the bitlines to be sensed by the sense amplifier should be in place, i.e., at the inputs of the sense amplifier, prior to receipt of the sense enable signal at the sense amplifier. Otherwise, the data may be missed by the sense amplifier. Also, the sense enable signal should arrive at the sense amplifier in a timely manner following receipt of the data to be sensed at the bitline inputs of the sense amplifier. Otherwise, an excessively delayed arrival of the sense enable signal at the sense amplifier may adversely affect memory performance, i.e., access speed, and correspondingly cause an unnecessary increase in memory power consumption. For example, a delay in shutdown of memory internal power-consuming activities, such as bitline discharge, may cause an unnecessary increase in memory power consumption. Therefore, it is necessary to control the timing of the sense enable signal to ensure that each sense amplifier of the computer memory is enabled in a timely manner after the appropriate data is available on the bitline inputs of the sense amplifier.